Digital amplifiers are typically employed for high efficiency applications for example audio amplification in portable devices such as personal stereos where battery life is a significant consideration. They are also used in high power amplification where the high efficiency means that the size and cost of the power supplies and heat sinks can be reduced. These amplifiers often utilise pulse width modulation (PWM) to drive a switching power stage. However the source signals are typically stored as encoded sampled signals on a carrier such as a CD-ROM or as MP3 tracks on a memory device for example. During playback, these digital encoded signals are error-corrected and decompressed to give a sequence of digital words, each representing the instantaneous value of the audio signal, a signal format known as Pulse Code Modulation (PCM) Hence some kind of PCM-PWM Converter is needed to convert the encoded signal samples into a two- or three-level PWM signal.
A schematic of a digital amplifier for digital audio and employing a PCM-PWM Converter is shown in FIG. 1, the amplifier comprising an over-sampling filter 1, a Converter 2, a power switch 3, a low pass filter 4, and a headphone or loudspeaker load 5.
The input is a series of PCM digital words representing the original analogue signal amplitude levels sampled at successive sample instants, typically at an audio sampling rate fs of 48 kHz or 44.1 kHz. The over-sampling or interpolation filter 1 adds additional samples from the incoming audio source samples by interpolating between the actual samples, thereby effectively increasing the sampling rate as is known, to an interpolated sampling rate fi of say 8 times fs. The over-sampled audio signal cin is fed to the Converter 2 which comprises a modulator to convert these words into a signal pwm_out comprising a series of pulses of varying width (PWM) suitable for switching the switching element 3, at a pulse repetition frequency (PRF) or PWM pulse frame rate fP, equal to fi, say. The power switch 3 switches a much larger output voltage into a low pass filter 4 which removes high-frequency components of this signal to give a smoothed analogue signal for applying to the headphone or speaker load 5. The switch element 3 outputs either a high level or a low level in the case of bi-level PWM or a high, mid-scale or low level in the case of tri-level PWM, and is switched at the high frequency fP with a duty cycle that is dependent on the sampled amplitude of the input signal.
A typical transistor switching bridge circuit for the switch element 3 is shown in FIG. 2, and comprises four MOSFET power transistors (T1–T4) arranged into two half bridges driving a load connected between output nodes B and C as shown and as is known and collectively referenced 3b. Bi-level operation is achieved by switching complementary transistors in each bridge on and off in pairs, for example T1 and T4 for one level, driving B high and C low, and T2 and T3 for the other level, driving B low and C high. In tri-level modulation, the mid-scale state is normally implemented by having the corresponding transistor from each half bridge either high or low at the same time—for example having both T1 and T2 on together, driving both B and C high, or T3 and T4, driving both B and C low, in each case giving zero differential output voltage. The detailed control of the gates of these four MOSFETs according to the high, mid-scale, or low output state requested by converter 2 is implemented in output control logic 3a inside power switch 3.
A tri-level waveform representing an analogue signal is shown in FIG. 3a. Tri-level modulation offers the advantage that the switching activity is halved with respect to bi-level modulation. This is because whenever a transition occurs, only one of the half-bridges changes state. Furthermore, tri-level modulation offers an absence of even order carrier components, as described for example in J Vanderkooy “New Concepts in Pulse-width Modulation” AES 97th Conference Preprint 3886 November 1994.
FIGS. 3b and 3c show the tri-level signalling for the switch element 3 of FIG. 2 in more detail. The top trace is the tri-level signal pwm_out from the converter 2 of FIG. 1. This is amplified as described above by independently controlling the half bridges of the switch 3. Thus for example controlling transistor T1 and T3 will control the voltage at node B; and similarly transistor T2 and T4 will control node C. Therefore with appropriate control of nodes B and C, the tri-level differential output signal A equal to B−C can be produced as an amplified version of pwm_out as is shown.
The PWM signal (A) shown represents a low-amplitude signal, so the high and low pulses are narrow. For an analogue PWM waveform, there would also be some extremely narrow pulses, but for a digital system the input level is quantised, so very small input levels will be rounded to exactly zero. Thus some pulse frames will have no pulse at all. In fact, for low amplitude signals, these zeros can be quite common. Given the “crest factor” of 20 dB or so in many audio sources, and the presence of quiet passages in most music, and the likely scenario where there is some upstream digital volume control attenuating the audio signal, rather than playing music at full volume, such low-amplitude signals are themselves quite common.
When a zero differential output is desired, either for the “off” part of a pulse frame, or for a whole pulse frame, there is a choice at every zero-going transition whether to turn both high-side devices (T1 and T2) on, or to turn both low-side devices (T3 and T4) on. FIGS. 3b and 3c show two different known schemes.
U.S. Pat. No. 6,614,297 discloses the switching scheme of FIG. 3c in which the choice is always to turn T3 and T4 on. This gives little common-mode signal, at least for low-level signals, and so can minimise some components of EMI. However this requires very short but accurate pulses, which are hard to achieve practically, especially when driving large high-current output devices because of the large narrow current pulses needed to drive the input capacitances of these output devices. In general, rather than instantaneously switching from off to a fixed on resistance, there will be a time during which the “on” resistance will still be ramping down to its asymptotic “on” resistance. Also, to avoid the risk of the upper FET, say, not being fully off before the lower FET is turned on, resulting in a high-current path between the supply rails, there is generally a deliberate delay introduced in the pre-driver circuitry. This ensures a delay between turning the upper FET off and turning the lower FET on and vice versa. However these precautions both narrow the resulting pulses and may cause narrow pulses to be swallowed altogether, causing a dead-band in the characteristic curve of output voltage versus input pulse width, analogous to the crossover distortion apparent in the typical output voltage versus input voltage characteristic of a Class AB or Class B amplifier output stage.
In addition, the load presented by the speaker 5 may have an inductive component and the low-pass filter 4 will usually be an L-C filter with an inductive component of impedance. Therefore during the interval when both devices are off, this inductive load will tend to fly past the positive or negative supply rail, depending on the inductor current. This waveform is caught by a diode rather than tied directly to the supply rail via a FET. Even if the characteristics of this diode are predictable the overshoot may still give some distortion of effective pulse width. In practice, whether on-chip or off-chip, the characteristics of these diodes will have a wide tolerance, uncorrelated with the electrical characteristics of other circuit elements and with a strong thermal dependence. Therefore the distortion will be unpredictable, foiling attempts to pre-distort to correct for it.
Furthermore, even if it were possible to drive the output devices very fast, the resulting fast edges could give troublesome high-frequency EMI components.
U.S. Pat. No. 6,211,728 discloses the switching scheme of FIG. 3b, in which the aforementioned choice is alternated every cycle. This avoids short pulses on either side, B or C, but gives rise to a common-mode full-amplitude square wave at half the sample frequency and odd harmonics thereof. This large common-mode signal is present even when the differential signal is small or even exactly zero and can give rise to excessive EMI in some applications. Also both sides switch once per cycle, even with zero signal. For small signals, with frequent “zeros”, this is wasteful of switching energy consumed by the pre-drivers driving the output device gates.
A further subtlety in implementation of tri-level PWM concerns the location of the transitions. In standard or single sided PWM, only the leading or trailing edge of the pulse varies with the input signal, the other edge being fixed. In double-sided PWM, both leading and trailing edge of the pulse vary in order that the PWM pulses are centred symmetrically around the PRF (Pulse-Repetition Frequency) clock. To first order, as long as the output is on for the required fraction of each cycle, it will generate the corresponding contribution to the output waveform. But second order effects, such as the signal-dependent skewing of the “centroid” of the output pulse relative to the clock, give rise to distortion mechanisms in the single-sided schemes. Double sided PWM is more complicated to implement, but results in reduced distortion when compared with single sided PWM. Known analog schemes such as those described in U.S. Pat. No. 6,262,632, U.S. Pat. No. 6,614,297, and U.S. Pat. No. 5,077,539 can generate the double-sided modulation quite easily, but digital sampled-data generation is not so straightforward, particularly when pulse lengths of odd numbers of clocks are required.
A schematic for a PWM converter is illustrated in FIG. 4, the converter 2 typically comprising a word length reduction (WLR) circuit 6 and a PWM modulator circuit 7 with the output qout of WLR 6 coupled to the input pwm_in of PWM modulator 7. Word length reduction circuits reduce the word length of the digital sample values, for example quantising these from 16 bits to 8 bits by eliminating the (8) least significant bits (LSB). They are typically implemented using sigma delta modulators (SDM) or noise shaper circuits. For economy of explanation, the terms noise shaper and SDM will be used interchangeably in this application since they refer to similar techniques, both used to shape the spectrum of output quantisation noise. The SDM arrangement shown uses a Word Length Reduction quantiser QWLR 12, a loop filter G(z) 11, and negative feedback to shape the spectrum of the extra quantisation noise generated, to move it away from the audio band up to higher frequencies. The feedback loop extends from the output of the quantiser 12 to the input of the WLR circuit 6 at adder 10. The reduced word length of the samples allows for reduced specification and hence cheaper modulators 7.
The PWM modulator 7 generates an output pwm_out with high, low and mid-scale states in tri-level applications. More precisely, in tri-level applications, the output pwm_out of PWM modulator 7 will typically comprise two or more parallel digital signals together indicative of the chosen one of these three states, which will then be translated by the output control logic (3a) within power switch 3 to generate the desired high-amplitude output signal to drive the load 5 via LP filter 4. But for economy of explanation we will refer to this signal pwm_out as a single tri-level signal. Signal pwm_out will generally consist of a string of pulses of high or low level, at the high frequency PWM pulse frame rate fP, with a pulse width that is proportional to the amplitude of the modulator's input signal pwm_in, and a polarity determined by the MSB or sign bit of pwm_in.
In the implementation of FIG. 4, the modulator 7 utilises an absolute value circuit block 13 as well as the modulator function block 14, to which the MSB of pwm_in provides a “sign” input and the absolute value block 13 provides a “count” input. The PWM function block 14 uses a digital counter (described hereafter as the ‘pulse width-counter’) clocked off a higher-frequency system clock or bit-clock of frequency fB, possibly 128 times fP, to produce a pulse-width proportional to the value of “count”. Depending on whether the pulse is centred within each pulse frame, or left-justified to the start of each pulse frame, either double- or single-sided modulation can be produced. Other modulator implementations could alternatively be used, for example using digital triangular waves to produce double-sided modulation, as is known, and described for example in U.S. Pat. No. 5,077,539. Similarly, a digital sawtooth waveform can be used to produce single-sided modulation.
As discussed above with reference to FIG. 3c, a problem with tri-level PWM is that at low signal levels the output pulse can be very short. This is because a signal close to zero is represented by an output which is predominantly zero, but with occasional short positive or negative pulses to represent the low-amplitude signal. An 8-bit noise shaper will produce 256 discrete amplitude levels, corresponding to 127 positive pulse widths and 128 negative pulse widths. With a typical pulse-repetition frequency of 352.8 kHz, the minimum pulse width is 1/(352800*128)=22 ns. Very short pulses are problematic for the output switching stage due to limitations in the feasible switching times associated with driving the MOSFETs, and also due to higher levels of EMI at high frequencies. Typical output stages are capable of transition times in the order of 10–30 ns, therefore the minimum pulse width will not be accurately represented, resulting in signal distortion and noise with low-amplitude inputs. One way of increasing the minimum pulse length is to reduce the resolution of the word length reduction circuit 6 by using a quantizer with fewer output bits. However, this introduces more quantisation noise and so has the effect of reducing SNR, unless much more aggressive and hence complex and costly noise-shaping architectures are used. On the other hand, the waveform scheme of FIG. 3b can cause EMI problems because of the common-mode energy and unnecessary power dissipation in the pre-drivers. So an improved waveform scheme with less common-mode and switching energy, but also with no requirement for such short pulses is desirable.